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  data brief for further information contact your local stmicroelectronics sales office. august 2011 doc id 022109 rev 1 1/12 12 STEVAL-IME003V1 STEVAL-IME003V1 demonstration board based on the sthv748 high voltage pulser features 4-channel outputs: high voltage and low voltage bnc connectors load simulator using signal equivalent circuits possibility to set up own load simulator 16 preset waveforms usb connector to connect stm32 with pc and supply power to it 4 mb serial flash memory to host fpga code and waveforms memory expansion connector to add external serial flash connectors to supply high voltage and low voltage to the sthv748 output stage leds to monitor the power management stage human machine interface to select, start and stop the generation of the preset waveforms 25 leds to monitor board behavior rohs compliant description the STEVAL-IME003V1 demonstration board is designed around the sthv748 4-channel high voltage pulser, a state-of-the-art device designed for ultrasound imaging applications. the output waveforms can be displayed directly on an oscilloscope by connecting the scope probe to the relative bncs. 16 preset waveforms are available to test the hv pulser under varying conditions. STEVAL-IME003V1 www.st.com
schematic diagrams STEVAL-IME003V1 2/12 doc id 022109 rev 1 1 schematic diagrams figure 1. STEVAL-IME003V1 hierarchical blocks !-v $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54 $!4!/54;= 4(3$?%. -#5?&0'!?'0)/;= $6$$ (60 (60 6$$0 (6- (6- 6$$- $6$$ (60 (60 6$$0 (6- (6- 6$$- "/!2$?0/7%2?",+ "/!2$?0/ 7%2 (60 (60 $6$$ 6$$0 6$$- (6- (6- 6&0'!?)/?6 6&0'!?#/2%?6 53"?$)3#/..%#4 53"?$- 53"?$0 &,!3(?6 -#5?6 34-?&,!3(?",+ 34-?&,!3( &,!3(?# &,!3(?$1 &,!3(?n3 &,!3(?$1 &,!3(?$1 &,!3(?$1 -#5?&0'!?/3#?%. -#5?&0'!?).)4?" -#5?&0'!?-/$% -#5?&0'!?3530%.$ &0'!?-#5?!7!+% &0'!?-#5?$/.% 53"?$)3#/..%#4 53"?$- 53"?$0 -#5?&0'!?02/' &,!3(?6 -#5?6 &0'!?'0)/;= &0'!?",+ &0'! 4(3$?%. &0'!?-#5?!7!+% -#5?&0'!?/3#?%. &0'!?30)?##,+ &0'!?30)?-/3) &0'!?30)?-)3/ &0'!?30)?-)3/ &0'!?30)?-)3/ &0'!?30)?3%, -#5?&0'!?).)4?" -#5?&0'!?02/' -#5?&0'!?-/$% &0'!?-#5?$/.% -#5?&0'!?3530%.$ 6&0'!?#/2%?6 6&0'!?)/?6 $!4!/54;= -#5?&0'!?'0)/;= -#5?&"'!?'0)/;= 34(6?",+ 34(6 )." ).! ).# ).# ).# ).$ ).$ ).$ ). ).! ).! )." )." (6- (6- (60 (60 $6$$ 6$$0 6$$- 4(3$?%.
STEVAL-IME003V1 schematic diagrams doc id 022109 rev 1 3/12 figure 2. STEVAL-IME003V1 fpga bank 0 configuration !-v 3/4 , #$etails $igikey   .$ 4$+#82*+ 0ackage  #$etails  $igi+ey   .$ !684!#,-84! 0ackage  60ower-anagement 23  -olex  53" 3/44 , 34(60ower-anagement *$etails 23  0hoenix#ontact -fg#ode-+$3  *$etails  23  0hoenix#ontact -fg#ode-+$3  *$etails 238  0hoenix#ontact -fg#od e -+$3  *$etail s 0hoenix#ontact-fg#ode-04  23  #and#$etai l 4$+#82*+ $igikey   .$ $imension %)!  #$etai l 4$+#82!+ $)')+%9   .$ $imension %)!  ,$etail 4$+6,&!4 2-2 23  # # # #$etails  $igikey   .$ 4$+#+'.83!- 0ackagemmxmm # # #$etails  $igikey   .$ 4$+#82#- 0ackage %)!  +ingbright+0352# 23  &arnell ,%$ 37$etails 23  +.)44%2 37)4#(--34 ./4!33%-",9 53"/. -# 5 &0' ! (60 (60  '. $ $6$ $ 6$$ 0 '.$ 6$$ - (6- (6-  '.$ ,/70/7%2 % ' ! 4 , / 6 ( ' ) ( 53"?6 $- $0 $0 $- 53"$0 53"$- 53"?$)3#/..%#4 (60 (60 $6$ $ 6$$0 6$$- (6- (6- 53"$- 53"?$)3#/..%#4 53"$0 53"?6 %84?6 (60 (60 $6$ $ 6$$0 6$$- (6- (6- -#5?6 6&0'!?)/?6 6&0'!?#/2%?6 53"?$)3#/..%#4 53"?$- 53"?$0 &,!3(?6 &,!3(?6 53"?6 53"?6 '.$?0/7%2 '.$?0/7%2 '.$?0/7%2 '.$?0/7%2 %84?6 '.$?3()%,$ $6$ $ # n 6 6 # n 6 6 $ 3-46! $ 3-46! # n & # n & # n 6 6 2  2  # u& 6 # u& 6 37 --34 37 --34 #/-?a  #/-?b  /.?a  /.?b  /.?a  /.?b  nc  nc  # n6 6 # 6 # u& # u& * 6 #onnector * 6 #onnector   $ 2%$ $ 2%$ # n 6 6 # n 6 6 # n& # n& * (60 * (60    5 53"5& 7 5 53"5& 7 $  'rd  $  $  6  $  5 343xx 5 343xx 6in  &"6o  %.  '.$  37  # n6 6 # n6 6 # n6 6 # #. 53"?mini" #. 6"53  $-  $0  )$nc  '.$  3(%,,  3(%,,  3(%,,  3(%,,  $ 2% $ $ 2% $ 2  2  2 - 2 - * ,6 * ,6     #  u  6 #  u  6 2 2 2 2 $ 2% $ $ 2% $ 2  5 ,$3-2 5 ,$3-2 6).  '.$  ).(  "903  6/54  , u( , u( # n 6 6 # n 6 # u   6 # u   6 * (6- * (6-    2  2    *  *   # u   6 # u   6 % ' ! 4 , / 6 ( ' ) (
schematic diagrams STEVAL-IME003V1 4/12 doc id 022109 rev 1 figure 3. STEVAL-IME003V1 fpga bank 1 configuration !-v *umper*isusedtocontrol)/pullupsduring&0'!configurat ion  /pendefault tofloat)/outputduring&0'!configuration  3etjumpertoenable)/pullupsduring&0'!configuration  $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r $iffpai r #and#$etails 4$+#82!+ $)')+%9   .$ $imension %)! *umpers* *and*areusedtosetdataoutoutputstate  #onfigure*and*tosetupoutputsidlestateasfollows   *and*open (igh :default  *closedand*open #lamp(62?3 7  *and*closed (igh :  *openand*closed #lam p /pen*default toconnect&0'!output s #lose*todisconnectoutputs(igh : ./4!33%-",9 ./4!33%-",9 ./4!33%-",9 4(%3%*5-0%23 (37!0%. 34(6)/#/..%#4/ 2 )$,%34!4 % &0'!$)3#/..%# 4 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4!/54;= (37!0%. 4(3$?%. #,+/54 42)''%2?/54 $!4! /54 4(3$?%. $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 $!4! /54 #,+/54 42)''%2?/54 ()?: )$,%?34!4% )$,%?34!4% 4(3$?%. $!4!/54;= 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 &0'! "ank 5! 8#3,8 #3'# 5! )/??,.?62%& # )/??,0?( 37!0%. $ )/??,. ! )/??,0 " )/??,. # )/??,0 $ )/??,. ! )/??,0 " )/??,. ! )/??,0 " )/??,. ! )/??,0 # )/??,. % )/??,0 & )/??,.?62%& ! )/??,0 " )/??,. % )/??,0 % )/??,. ! )/??,0 # )/??,. # )/??,0 $ )/??,. & )/??,0 ' )/??,. ! )/??,0 " )/??,.?'#,+ # )/??,0?'#,+ $ )/??,.?'#,+ ! )/??,0?'#,+ " )/??,.?'#,+ #  )/??,0?'#,+ $  )/??,.?'#,+ ! )/??,0?'#,+ #  )/??,.?62%& & )/??,0 ' )/??,. ! )/??,0 " )/??,. & )/??,0 ' )/??,. ! )/??,0 " )/??,. % )/??,0 &  )/??,. #  )/??,0 $  )/??,. ! )/??,0 # )/??,. % )/??,0 &  )/??,.?62%& ! )/??,0 " )/??,.?3#0 % )/??,0?3#0 & )/??,.?3#0 ! )/??,0?3#0 #  )/??,.?3#0 #  )/??,0?3#0 $ )/??,.?3#0 ! )/??,0?3#0 " # n  # n  # u &6 # u &6 * *5-0%2 * *5-0%2   2 +  * (%!$%2 8 * (%!$%2 8                                     *  *   # n # n   *   *     *   *   # u&6 # u&6 2 +  2 +  2 + 2 + 
STEVAL-IME003V1 schematic diagrams doc id 022109 rev 1 5/12 figure 4. STEVAL-IME003V1 fpga bank 2 configuration !-v 37 37 37 $etails23  0lace2 closetotheclock source$3,5 device '2%%.,%$ +ingbright+0352# 23  &arnell ,%$ 0%2)0(%22!,-/$5,%0-/$ 053("544/. 3 #42,,% $ -(:%84%2.!,/3#),,!4/2 4woright angle  pinxfemale 0eripheral -odule0-/$ headers* * areinterfacedtothe &0'! witheachheaderproviding6power ground andeight)/gs4heseheadersmaybeutilizedas general purpose)/sormaybeusedtointerfaceto 0-/$s*and*areplacedincloseproximityg centers onthe0#"inordertosupportdual0-/$s # # #and#$etail 4$+#82!+ $)')+%9   .$ $imension %)!  $8 38 "!#+50/&5 ./4!33%-",9 ./4!33%-",9 .ear34!24button .ear34/0button )$,%statesignal %22/2signal 7henusingbackuposcillator8 2havetobemountedand2 mustbeunplaced 0-/$ 0-/$ 02/'2!- 34/ 0 &0'!2%3% 4 34!2 4 )$, % %22/ 2 &0'!53%2) / -(:/3# 2%$,%$ +ingbright+0352# 23  &arnell ,%$ 34!24 ?0" 34/0?0" &0'!?2%3%4 3%,?02/'?0" #42,?,%$ #42,?,%$ #42,?,%$ #42,?,%$ &0'!?#,+?-(: &0'!?$/54?"539 &0'!?!7!+% &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 #42,?,%$ #42,?,%$ #42,?,%$ #42,?,%$ &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?0-/$?0 &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?53%2?)/? &0'!?#,+?-(: &0'!?2%3%4 34!24 ?0" 3%,?02/'?0" 34/0?0" &0'!?-#5?!7!+% -#5?&0'!?/3#?%. -#5?&0'!?/3#?%. 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 # n & # n & 2 +  2 +  37 37053("544/. $034 37 37053("544/. $034 2  2 2  2 # n & # n & 8 8 /%34  '.$  6##  /54  37 37053("544/. $034 37 37053("544/. $034 $ '2%% . $ '2%% . 5 $3,5  5 $3,5  6##  6##  nc  nc  /54  '.$  '.$  0$.  * (%!$%2 8 * (%!$%2 8             37 37053("544/. $034 37 37053("544/. $034 # u &6 # u &6 $ '2%% . $ '2%% . # n & # n & * (%!$%2 8 * (%!$%2 8             37 37053("544/. $034 37 37053("544/. $034 # n & # n & 2 2 2 2 # n & # n & 40 4%340/).4 40 4%340/).4  &0'! "ank 5" 8#3,8 #3'# 5" 8#3,8 #3'# )/??,.?!?62%& &  )/??,0?! &  )/??,.?!?-! #  )/??,0?!?-! # )/??,.?!?-! '  )/??,0?!?-2%3%4 &  )/??,.?!?-! $ )/??,0?!?-#+% $ )/??,.?!?-! '  )/??,0?!?-! ( )/??,.?!?-! % )/??,0?!?-! % )/??,.?!?-"! + )/??,0?!?-7% + )/??,.?!?-! & )/??,0?!?-! & )/??,.?!?-"! (  )/??,0?!?-"! (  )/??,.?!?-! (  )/??,0?!?-! (  )/??,.?!?-#,+. ' )/??,0?!?-#,+ ' )/??,.?-/$4 + )/??,0?-! *  )/??,.?'#,+?-! ,  )/??,0?'#,+?-! ,  )/??,.?'#,+?-#!3. + )/??,0?'#,+?)2$9?-2!3. + )/??,.?'#,+?42$9?-,$- , )/??,0?'#,+?-5$- ,  )/??,.?'#,+?-$1 (  )/??,0?'#,+?-$1 (  )/??,.?!?-$1 *  )/??,0?!?-$1 *  )/??,.?!?-,$13. + )/??,0?!?-,$13 + )/??,.?&/%?"?-$1 ,  )/??,0?&#3?"?-$1 ,  )/??,.?,$#?-$1 - )/??,0?&7%?"?-$1 - )/??,.?-$1 . )/??,0?($#?-$1 . )/??,.?-$1 0 )/??,0?-$1 0 )/??,.?-5$13. .  )/??,0?-5$13 .  )/??,.?-$1 4 )/??,0?-$1 4 )/??,.?-$1 5 )/??,0?-$1 5  )/??,.?62%& .  )/??,0 - )/??,. - )/??,0 , )/??,.?$/54?"539 0 )/??,0?!7!+% 0 2 2 2 2 * (%!$%2 8 * (%!$%2 8                                 2 +  2 +  $ 2% $ $ 2% $ # u&6 # u&6 # n & # n & 2 k $.0 2 k $.0 # n & # n & $ '2%%. $ '2%%. 2 + 2 + 2 + 2 + # n & # n & # u&6 # u&6 2  2 2  2 2 +  2 +  # n & # n & 2 2 2 2 # n & # n & # u &6 # u &6
schematic diagrams STEVAL-IME003V1 6/12 doc id 022109 rev 1 figure 5. STEVAL-IME003V1 fpga bank 3 configuration !-v +ingbright+0 39# 23  ,%$ 30)%84%2.!,02/'2!--).'(%!$%2 30)&,!3(#42,3)'.!,3 0lace2closetothe&0'!device #onfigurationmodeselection &0'!?-/$%0arallel,ow or3erial(igh &0'!?-/$%-aster,ow or3lave(igh &0'!#/.&)'52!4)/ . 7hen&0'!?).)4?"bidirectionalopen drain is,owtheconfigur ationmemoryi s beingcleared  7henheld,ow thestartofconfigurationisdelayed  $uringconfiguration a,owonthisoutputindicatesthataco nfigurationdat a errorhasoccurred #$etails 4$+#82!+ $)')+%9   .$ $imension %)! %8430) &,!3( 0lace$ closeto* 02/' 02/'  02/'  02/'  02/'  02/'  02/' 02/'  02/'  02/'  02/'  02/' 02/'  02/' 02/'  02/'  02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ 02/'?,%$ &0'!?-/$% ##,+ &0'!?30)?-)3/ &0'!?30)?-)3/ &0'!?30)?-/3) &0'!?).)4?" &0'!?30)?3%, &0'!?30)?-)3/ ##,+ &0'!?30)?-)3/ &0'!?30)?-/3) &0'!?30)?3%, &0'!?30)?-)3/ &0'!?-/$% &0'!?-/$% &0'!?).)4?" &0'!?-/$% -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/ -#5?&0'!?'0)/;= &0'!?30)?-)3/ &0'!?30)?##,+ &0'!?30)?-/3) &0'!?30)?-)3/ &0'!?30)?-)3/ &0'!?30)?-)3/ &0'!?30)?3%, -#5?&0'!?).)4?" -#5?&0'!?02/' -#5?&0'!?-/$% -#5?&0'!?'0)/;= 6&0'!?)/?6 6&0'!?)/?6 2  2 2  2 2  2 2  2 $ 9%,,/7 $ 9%,,/7 * #/.  * #/.            2  2 2  2 2  2 2  2 2  2 2  2 $ 9%,,/7 $ 9%,,/7 2 .! 2 .! &0'! "ank 5# 8#3,8 #3'# 5# 8#3,8 #3'# )/??,.?-?#-0-)3/ 4 )/??,0?##,+ 2  )/??,.?#-0-/3) 6 )/??,0?#-0#,+ 5  )/??,.?-/3)?#3)?"?-)3/ 4 )/??,0?$?$).?-)3/?-)3/ 2  )/??,. 6 )/??,0 5  )/??,.?$?-)3/ 6 )/??,0?$?-)3/ 4 )/??,.?$ 0 )/??,0?- .  )/??,.?$ 6 )/??,0?$ 5  )/??,. .  )/??,0 - )/??,.?62%& 4 )/??,0 2  )/??,. 6 )/??,0 4 )/??,. 0 )/??,0 . )/??,. . )/??,0 - )/??,. 6 )/??,0 5  )/??,.?'#,+ 4 )/??,0?'#,+ 2  )/??,.?'#,+?53%2##,+ 6 )/??,0?'#,+?$ 5  )/??,.?'#,+?$ 4 )/??,0?'#,+?$ 2 )/??,.?'#,+ 6 )/??,0?'#,+ 4 )/??,. . )/??,0 - )/??,.?62%& 6 )/??,0 5 )/??,. 6 )/??,0 5 )/??,. 0 )/??,0 . )/??,. 6 )/??,0 4 )/??,. 4 )/??,0 2 )/??,. 0 )/??,0 . )/??,.?2$72?"?62%& 4 )/??,0?$ 2 )/??,.?$ 6 )/??,0?$ 5 )/??,.?$ 4 )/??,0?$ 2 )/??,. 6 )/??,0 4 )/??,.?$ 0 )/??,0?$ . )/??,.?#3/?" 6 )/??,0?).)4?" 5 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 2 .! 2 .! 2 + 2 + 2  2 2  2 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 2 +$.0 2 +$.0 2  2 2  2 2 + 2 + 2  2 2  2 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 2  2 2  2 2 2 2 2 2 2 2 2 2 +  2 +  2  2 2  2 $ 9%,,/7 $ 9%,,/7 # n & # n & 2 +$.0 2 +$.0 $ 9%,,/7 $ 9%,,/7 2  2 2  2 # u &6 # u &6 2  2 2  2 $ 9%,,/7 $ 9%,,/7 2  2  $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 40 4%340/).4 40 4%340/).4  2  2 2  2 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 $ 9%,,/7 2  2 2  2 $ '2%% . $ '2%% . 2  2 2  2
STEVAL-IME003V1 schematic diagrams doc id 022109 rev 1 7/12 figure 6. STEVAL-IME003V1 fpga bank 3 configuration !-v &0'!banknotused &0'! "ank 5$ 8#3,8 #3'# 5$ 8#3,8 #3'# )/??,.?62%& . )/??,0 . )/??,. 0 )/??,0 0 )/??,.?62%& - )/??,0 , )/??,.?-$1 5 )/??,0?-$1 5 )/??,.?-$1 4 )/??,0?-$1 4 )/??,.?-5$13. 0 )/??,0?-5$13 0 )/??,.?-$1 . )/??,0?-$1 . )/??,.?-$1 - )/??,0?-$1 - )/??,.?-$1 , )/??,0?-$1 , )/??,.?-$1 + )/??,0?-$1 + )/??,.?-,$13. , )/??,0?-,$13 , )/??,.?-$1 * )/??,0?-$1 * )/??,.?'#,+?-$1 ( )/??,0?'#,+?-$1 ( )/??,.?'#,+?-,$- + )/??,0?'#,+?42$9?-5$- + )/??,.?'#,+?)2$9?-#!3. + )/??,0?'#,+?-2!3. , )/??,.?'#,+?-! ( )/??,0?'#,+?-! ( )/??,.?-/$4 + )/??,0?-! , )/??,.?-#,+. ' )/??,0?-#,+ ' )/??,.?-! * )/??,0?-! * )/??,.?-"! & )/??,0?-"! & )/??,.?-! ( )/??,0?-! ( )/??,.?-"! % )/??,0?-7% % )/??,.?-! & )/??,0?-! & )/??,.?-! $ )/??,0?-! $ )/??,.?-! ' )/??,0?-#+% ( )/??,.?-! $ )/??,0?-2%3%4 % )/??,.?-! & )/??,0?-! & )/??,.?62%& # )/??,0 #
schematic diagrams STEVAL-IME003V1 8/12 doc id 022109 rev 1 figure 7. STEVAL-IME003V1 fpga power and configuration !-v &0'!"!.+ ./453% $ 23  *umper*usedtoprevent&0'!from programmingfromconfigurationsource 3ettodisable&0'!programming /pendefault toenable&0'! programming % . / $ " ? - ! 2 ' / 2 0 *umper* toforce &0'!into suspendmode $efault toallow-#5 tocontrol &0'!suspend mode &0'!*4! '  2esistor!rray xmm .ot!ssembly 8ilinx0arallel)6#onnector mmxshroudedheader 3530%.$#-0#3?" # # # # #$etails -urata'2-#2*-%, $igikey   .$ $imension %)! # # # # # # # # # # #$etail s 4$+#82*+ $igikey   .$ $imension %)! 4obeplaced near5 4obeplaced near5 2%3$)08 ./4!33%-",9 3530%.$ &0'!02/ ' $)3!",% &0'!*4! ' $/. % &0'!02/ ' ./4!33%-",9 ./4!33%-",9 ./4!33%-",9 ./4!33%-",9 &0'!?02/' &0'!?$/.% &0'!?02/' &0'!?3530%.$ &0'!?$/.% &0'!?#-0?#3?" &0'!?4$) &0'!?4-3 &0'!?4#+ 6&0'!?)/?6 6&0'!?#/2%?6 &0'!?4$/ -#5?&0'!?02/' &0'!?-#5?$/.% -#5?&0'!?3530%.$ 6&0'!?)/?6 6&0'!?#/2%?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?#/2%?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 6&0'!?)/?6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 2 +  2 +  * #/. ! * #/. !               2 2 2 2 # u&6 # u&6 2. 2%3)34/2$)0  2. 2%3)34/2$)0          # u &6 # u &6 2 + 2 + # u&6 # u&6 2 2 2 2 * *5-0%2 * *5-0%2   # n& # n& # u&6 # u&6 * (eader * (eader    # u&6 # u&6 5 , 8'#42 5 , 8'#42      # u &6 # u &6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 5  6'#42 5  6'#42      # u &6 # u &6 # u&6 # u&6 2 2 2 2 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 2  2  1 . 1 . # u&6 # u&6 # u&6 # u&6 2  2  # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 # n & # n & 2 + 2 + 2 2 2 2 # u&6 # u&6 234 37053("544/. $034 234 37053("544/. $034 $ 344 (! $ 344 (! # u&6 # u&6 &0'! 0ower#onfiguration 5% 8#3,8 #3'# 5% 8#3,8 #3'# 4#+ ! 4-3 " 4$/ $  4$) $ 02/'2!-?"? 6 3530%.$ 2 $/.%? 6 #-0#3?"? 0 6##/? " 6##/? " 6##/? " 6##/? $  6##/? $ 6##/? % 6##/? % 6##/? '  6##/? *  6##/? *  6##/? - 6##/? 2  6##/? 0 6##/? 2  6##/? 2 6##/? 5  6##/? 5 6##/? 5 6##/? % 6##/? ' 6##/? * 6##/? * 6##/? - 6##/? 2 6##!58 " 6##!58 " 6##!58 % 6##!58 % 6##!58 % 6##!58 '  6##!58 * 6##!58 + 6##!58 - 6##!58 0 6##!58 0 6##!58 0 6##).4 ' 6##).4 (  6##).4 ( 6##).4 * 6##).4 * 6##).4 + 6##).4 + 6##).4 ,  6##).4 , 6##).4 - 6##).4 - '.$ ! '.$ " '.$ # '.$ $ '.$ $ '.$ " '.$ # '.$ ' '.$ ' '.$ ' '.$ (  '.$ ( '.$ * '.$ * '.$ * '.$ % '.$ '  '.$ + '.$ , '.$ , '.$ - '.$ - '.$ - '.$ . '.$ 2 '.$ 2 '.$ 2  '.$ 2 '.$ 2 '.$ 4  '.$ 5  '.$ 5 '.$ 6 '.$ 6 '.$ + '.$ * '.$ ! # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 2 2 2 2 # u&6 # u&6 # u&6 # u&6 # u&6 # u&6 2 +  2 +  2 +  2 +  # u&6 # u&6 # u &6 # u &6 # u&6 # u&6 $ '2%% . $ '2%% .
STEVAL-IME003V1 schematic diagrams doc id 022109 rev 1 9/12 figure 8. STEVAL-IME003V1 configuration of the sthv748 !-v # # # #$etails $igi+ey   .$ -urata'2-2!+!$ * * * * * * *and*$etail s 4yco%lectronics   23  * * * * * * *and*$etail s 4yco%lectronics   23  34(6 4(3$ # ? 4 5 / 6 , " ? 4 5 / 6 , ! ? 4 5 / 6 , 8$#2?! 8$#2?# 8$#2?" 4(3 $ $ $ $ $ $ $ $ $ diode$&,3rs code   (6- (60 ).! ).! ).! (6- (6- 6$$0 6$$- (60 (6- ). (6- (6- )." (6- ).$ (60 )." ).! ).$ (60 )." (60 (6- ).$ (6- 6$$- ).! ).! 6$$0 )." $6$ $ ).# ).# ).# )." )." ).# ).# ).# ).$ (60 ).$ ).$ ). $6$ $ (60 (60 $6$ $ 6$$0 6$$- (6- (6- 4(3$?%. $6$ $ 4(3$?%. (60 (6- (60 (6- (60 (6- (6- (60 )." ).! ).# ).# ).# ).$ ).$ ).$ ). ).! ).! )." )." (6- (6- (60 (60 $6$ $ 6$$0 6$$- 4(3$?%. # p6 # p6 #  n #  n * " 3 * " 3   # . ! # . ! 2  k 2  k * "3 * "3   * ". # * ". #   2 .! 2 .! # p 6 # p 6 * ". # * ". #   # n # n # n # n $ $&,3 $ $&,3 # .! # .! # p # p * #/. * #/.    $ $&,3 $ $&,3 # n # n #  n #  n # n # n $ $&,3 $ $&,3 # p 6 # p 6 * ".# * ".#   2 .! 2 .! 2   2   $ $&,3 $ $&,3 * "3 * "3   * "3 * "3   # n # n #  n #  n # n # n * ".# * ".#  * ". # * ". #   #  n #  n * "3 * "3   5 34(6 5 34(6 !'.$  2ef(6-  (6-?!  (6-?!  (6/54?!  (60!  2ef(60  (60?!  (60?"  2ef(60  (60?"  (6/54?"  (6-?"  (6-?"  2ef(6-  $?#42,  ).  ).?"  ).?"  ).?"  6$$0  '.$07  8$#2?"  ,6/54? "  ,6/54? #  8$#2?#  '.$07  6$$-  ).?#  ).?#  ).?#  4(3$  !'.$  2ef(60  (60?#  (60?$  2ef(60  (60?$  (6/54?$  (6-?$  (6-?$  2ef(6-  $'.$  (60?#  $6$ $  ).?$  ).?$  ).?$  6$$0  '.$07  8$#2?$  ,6/54? $  ,6/54? !  8$#2?!  '.$07  6$$-  ).?!  ).?!  ).?!  %.  35"  2ef(6-  (6-?#  (6-?#  (6/54?#  # . ! # . ! 2  k 2  k 2 k 2 k #  n #  n # n # n 40 4%34 0/).4 40 4%34 0/).4  #  n #  n * " 3 * " 3   # p # p * ". # * ". #   2 . ! 2 . ! #  n #  n 2  2  # n # n 2   2   * " 3 * " 3   $ $&,3 $ $&,3 # .! # .! # n # n #  n #  n # n # n * "3 * "3   # n # n 2   2   2 .! 2 .! # n # n #  n #  n #  n #  n #  n #  n #  n #  n $ $&,3 $ $&,3 * " 3 * " 3   * " 3 * " 3   #  n #  n * "3 * "3   * ". # * ". #   # p # p # p # p # n # n # p6 # p6 #  n #  n # n # n $ $&,3 $ $&,3 #  n #  n * "3 * "3   #  n #  n * ". # * ". #  $ $&,3 $ $&,3  
schematic diagrams STEVAL-IME003V1 10/12 doc id 022109 rev 1 figure 9. STEVAL-IME003V1 configuration of the stm32 !-v .ot!ssembly 23  #+9"&0 +ingbright+0352# 23  &arnell ,%$ *4!'37 $ -ale#onnectorx 0itchmm 3!-4%#&43(   & $ + +ingbright+0352# 23  &arnell ,%$ -urata#34#%-' 2 $igi+ey   .$ 23  &arnell  /3#),,!4/ 2 0lacenear-#5 -#5 /04)/.!,&0'!)/ 30)&,!3 ( /04)/.!,&0'!#/.&)'52!4)/.3)'.!, 3 5se*toenabledisablepowerfor30)flashdevice *mustbeopenwhenusingexternalspiflashdeviceon connecto*$efaultvalueclosed #$etails $igikey   .$ 4$+#82*+ 0ackage ).430)&,!3( &,!3($)3!", % -#52%3% 4 -(:/3# $/7.,/! $ &,!3(2%!$9 -#5*4! ' 34-& 2%3%4 53%2?,%$ *.4234 *4$/ *4-3 *4$) *4#+ 2%3%4 53%2?,%$ 53%2?,%$ 53%2?,%$ /3#/54 /3#). "//4 "//4 /3#). &,!3(?n3 &,!3(?# &,!3(?$1 &,!3(?$1 *4-3 *4#+ *4$) *4$/ *.4234 2%3%4 /3#/54 34-?'0)/? 34-?'0)/? &,!3(?$1 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? &,!3(?$1 &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ &0'!?'0)/ 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? &0'!?'0)/;= 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? &0'!?-#5?!7!+% &0'!?-#5?$/.% -#5?&0'!?/3#?%. -#5?&0'!?).)4?" -#5?&0'!?-/$% -#5?&0'!?02/' -#5?&0'!?3530%.$ 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? 34-?'0)/? $-?34- 53"?$)3#/..%#4 $0?34- 6$$! -#5?6 &,!3(?6 &,!3(?$1 &,!3(?$1 &,!3(?# &,!3(?n3 &,!3(?$1 &,!3(?$1 &,!3(?# &,!3(?$1 &,!3(?n3 &,!3(?$1 &,!3(?$1 &,!3(?$1 &0'!?'0)/;= -#5?&0'!?/3#?%. -#5?&0'!?).)4?" -#5?&0'!?-/$% -#5?&0'!?3530%.$ &0'!?-#5?!7!+% &0'!?-#5?$/.% 53"?$)3#/..%#4 53"?$- 53"?$0 -#5?&0'!?02/' -#5?6 &,!3(?6 -#5?6 -#5?6 -#5?6 -#5?6 -#5?6 &,!3(?6 -#5?6 2 k 2 k 2  2  2 2 .! 2 2 .! # u &6 # u &6 # n & # n & # n & # n & 2 2 .! 2 2 .! 2  + 2  + $ 2% $ $ 2% $ 2 2 .! 2 2 .! 2 2 .! 2 2 .! 2 k 2 k # n & # n & 9 -(z 9 -(z 2 2 .! 2 2 .! 2  k 2  k 2 k 2 k * 37$*4!' * 37$*4!'           2 + 2 + 2 2 .! 2 2 .! # n& # n& 2 2 .! 2 2 .! $ 2% $ $ 2% $ 2  k 2  k 2 + 2 + 2 2 .! 2 2 .! $ 2% $ $ 2% $ 2 k 2 k 2 2 .! 2 2 .! 5 .1x3# 5 .1x3# 6##  $1  633  #  n3  n76pp$1  n(/,$$1  $1  2 2 .! 2 2 .! 2 2 2 2 # n& # n& 2 k 2 k 234 37053("544/. $034 234 37053("544/. $034 2 2 .! 2 2 .! # n& # n& 2 2 .! 2 2 .! 2 2 .! 2 2 .! *0 *5-0%2 *0 *5-0%2   2 2 2 2 5 34-&#4 5 34-&#4 6"!4  0# 4amper 24#  0# /3#?).  0# /3#?/54  0$/3#?).  0$/3#?/54  .234  633!  6$$!  0!  7 + 5 0  0!   0!   0!   0!   0!   0!   0!   0"  0"  0" "//4  0"  0"  633?  6$$?  0"  0"  0"  0"  0!   0!   0!    0!    0!    0! *4-3  633?  6$$?  0! *4#+  0! *4$)  0"*4$/  0"*.4234  0"  0"  0"  "//4  0"  0"  633?  6$$?  2 2 .! 2 2 .! 2 2 .! 2 2 .! # n& # n& * *   2 2 .! 2 2 .! 2  k 2  k
STEVAL-IME003V1 revision history doc id 022109 rev 1 11/12 2 revision history table 1. document revision history date revision changes 11-aug-2011 1 initial release.
STEVAL-IME003V1 12/12 doc id 022109 rev 1 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2011 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com


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